This invention relates generally to I/O circuitry in integrated circuit (“IC”) devices. In particular, this invention relates to a via-programmable design for I/O circuitry in IC devices that reduces the amount of ground bounce and power (i.e., “VCC”) sag of such devices.
Ground bounce and VCC sag are two well-known analog phenomena that are unavoidably encountered in the design of digital integrated circuit devices. Substantial ground bounce arises when the data signals on numerous active I/O pins on an IC device simultaneously switch from a logic 1 to a logic 0. Due to the sudden transition in the logic signals, a sudden rush of excess current (that was previously stored in the load capacitors of the I/O pins) flows from each of the I/O pins to the ground of the IC device. And since the return current path for the excess current includes several inductances (e.g., a bond wire/substrate inductance, a lead frame/pin inductance, and a board inductance), a voltage difference is generated between the IC device ground signal and the ground signal of the printed circuit board (“PCB”) of the IC device, according to the relationship V=L×(di/dt). As the rush in current builds and recedes, then, the IC device ground signal bounces. VCC sag, on the other hand, refers to the opposite phenomenon that occurs when numerous active I/O pins switch simultaneously from a logic 0 to a logic 1. Specifically, the sudden rush of current into the I/O pins, coupled with the inductances of the associated current path from the VCC source of the IC device to the I/O pins, temporarily pulls down the device VCC signal.
The noise in IC devices caused by ground bounce and VCC sag have become more of a problem in modern semiconductor devices, which are characterized by ever-increasing clock speeds and numbers of I/O pins. Due to such aberrations in device ground and VCC signals, then, the integrity of I/O signals in such devices have been reduced, resulting in errors in data transmission.
There are currently various design methods and IC device features that are employed to address the problem of ground bounce and VCC sag. For example, ICs are commonly designed with less inductive types of device packaging, slower slew rates, delay circuitry to reduce the number of simultaneously switching I/O pins, and different termination schemes to reduce the amount of current flow caused by switching I/O pins. Also, IC designers tend to design IC devices that operate using, for example, synchronous timing and low-voltage differential signaling (“LVDS”) to further limit the amount of ground bounce and VCC sag experienced by such devices. Despite these techniques, ground bounce and VCC sag continues to be a problem, especially in view of increasing clock speeds and numbers of I/O pins, and therefore IC designers continue to look for improvements that can be made in this area.